184 PIN DDR333 Registered DIMM

512MB With 32Mx8 CL2.5

AC Timing Parameters & Specifications

(These AC characteristics were tested on the Component)

Parameter Symbol Min Max Unit Note

Row cycle time tRC 60 ns

Refresh row cycle time tRFC 72 ns

Row active time tRAS 42 70K ns

/RAS to /CAS delay tRCD 18 ns

Row active to Row active delay tRP 18 ns

Row active to Row active delay tRRD 12 ns

Write recovery time tWR 15 ns

Last data in to Read command tWTR 1 tCK

Col. Address to Col. Address delay tCCD 1 tCK

Clock cycle time tCK 6 12 ns

Clock high level width tCH 0.45 0.55 tCK

Clock low level width tCL 0.45 0.55 tCK

DQS-out access time from CK /CK tDQSCK -0.6 0.6 ns

Output data access time from CK /CK tAC -0.7 0.7 ns

Data strobe edge to output data edge tDQSQ 0.45 ns

Read Preamble tRPRE 0.9 1.1 tCK

Read Postamble tRPST 0.4 0.6 tCK

CK to valid DQS-in tDQSS 0.75 1.25 tCK

DQS-in setup time tWPRES 0 ns 2

DQS-in hold time tWPREH 0.25 tCK

DQS falling edge to CK rising-setup time tDSS 0.2 tCK

DQS falling edge from CK rising-hold time tDSH 0.2 tCK

DQS-in high level width tDQSH 0.35 tCK

DQS-in low level width tDQSL 0.35 tCK

DQS-in cycle time tDSC 0.9 1.1 tCK

Address and Control input setup time tIS 0.8 ns

Address and Control input hold time tIH 0.8 ns

Data-out high-impedance time from CK, /CK tHZ -0.7 0.7 ns

Data-out low-impedance time from CK, /CK tLZ -0.7 0.7 ns

Mode register set cycle time tMRD 12 ns

DQ & DM setup time to DQS tDS 0.45 ns

DQ & DM hold time to DQS tDH 0.45 ns

DQ & DM input pulse width tDIPW 1.75 ns

Exit self refresh to read command tXSRD 200 tCK

Refresh interval time tREFI 7.8 us 1

Clock half period tHP

tCLmin or

tCHmin

DQS write postamble time tWPST 0.4 0.6 tCK 3

Note: 1. Maximum burst refresh of 8

2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown

(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a

previous write was in progress, DQS could be High at this time, depending on tDQSS.

3. The Maximum limit for this parameter is not a device limit. The device will operate with a great value for this

parameter, but system performance (bus turnaround) will degrade accordingly.

Transcend Information Inc.

1 2 3 4 5 6 7 8 9 10 11

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Frequency Inverter: Full I/O

Operating Instructions

(13466183)

Contents

About These Instructions

Safety information

1 Safety Information

Safety Information

Technical data

2 Technical Data

Installation

3 Installation

Commissioning

4 Commissioning

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Transcend TS64MDR72V3F Datový list Strana 8

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