Transcend TS64MSS64V6L Datový list

Procházejte online nebo si stáhněte Datový list pro Paměťové moduly Transcend TS64MSS64V6L. Transcend 512MB SDRAM 144Pin SO-DIMM PC133 Unbuffer Non-ECC Memory Uživatelská příručka

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T
T
T
S
S
S
6
6
6
4
4
4
M
M
M
S
S
S
S
S
S
6
6
6
4
4
4
V
V
V
6
6
6
L
L
L
144PIN PC133 Unbuffered SO-DIMM
512MB With 32M X 8 CL3
Description
The TS64MSS64V6L is a 64M bit × 64 Synchronous
Dynamic RAM Small Outline Dual In-line Memory Module
(S.O.DIMM), mounted 16 pieces of 256-Mbit SDRAM sealed
in sTSOP package and 1 piece of serial EEPROM (2-kbit)
for Presence Detect (PD). An outline of the products is
144-pin Zig Zag Dual tabs socket type compact and thin
package. Therefore, they make high.
Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operation frequencies, programmable
latencies allow the same device to be useful for a variety of
high bandwidth, high performance memory system
applications.
Features
Performance Range: PC-133
Conformed to JEDEC Standard 2 clocks.
Burst Mode Operation.
Auto and Self Refresh.
CKE Power Down Mode.
DQM Byte Masking (Read/Write)
Serial Presence Detect (SPD) with serial EEPROM
LVTTL compatible inputs and outputs.
Single 3.3V ± 0.3V power supply.
MRS cycle with address key programs.
Latency (Access from column address)
Burst Length (1,2,4,8)
Data Sequence (Sequential & Interleave)
All inputs are sampled at the positive going edge of
the system clock.
DRAM brand: Promos.
Operating Temperature TA: 0~70 °C
Symbol Function
A0~A12, BA0,BA1
Address input
DQ0~DQ63, Data Input / Output.
CLK0, CLK1
Clock Input.
CKE0, CKE1
Clock Enable Input.
/CS0~/CS3
Chip Select Input.
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
DQM0~DQM7
Data (DQ) Mask
SA0~SA2
Address in EEPROM
SCL
Serial PD Clock
SDA
Serial PD Add/Data input/output
Vcc
+3.3 Voltage Power Supply
Vss
Ground
NC
No Connection
Pin Identification
Transcend information Inc.
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Shrnutí obsahu

Strany 1 - A: 0~70 °C

TTTSSS666444MMMSSSSSS666444VVV666LLL 144PIN PC133 Unbuffered SO-DIMM512MB With 32M X 8 CL3 Description The TS64MSS64V6L is a 64M bit × 64 Synchronous

Strany 2

TTTSSS666444MMMSSSSSS666444VVV666LLL 144PIN PC133 Unbuffered SO-DIMM512MB With 32M X 8 CL3 31 Density of Each Bank on Module 1row of 256MB 40 32 C

Strany 3

TTTSSS666444MMMSSSSSS666444VVV666LLL 144PIN PC133 Unbuffered SO-DIMM512MB With 32M X 8 CL3 Dimension: ABCDEFGHIJK PCB: 09-2260 Side Millimeters

Strany 4

TTTSSS666444MMMSSSSSS666444VVV666LLL 144PIN PC133 Unbuffered SO-DIMM512MB With 32M X 8 CL3 Pinouts: Pin No Pin Name Pin No Pin Name Pin No Pin Nam

Strany 5

TTTSSS666444MMMSSSSSS666444VVV666LLL 144PIN PC133 Unbuffered SO-DIMM512MB With 32M X 8 CL3 Block Diagram A0~A12D0~D63BA0~BA1/RAS/CAS/WE/CS0CKE0CLK0

Strany 6 - Transcend information Inc

TTTSSS666444MMMSSSSSS666444VVV666LLL 144PIN PC133 Unbuffered SO-DIMM512MB With 32M X 8 CL3 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Vo

Strany 7

TTTSSS666444MMMSSSSSS666444VVV666LLL 144PIN PC133 Unbuffered SO-DIMM512MB With 32M X 8 CL3 Parameter Symbol Test Condition CAS Latency Value(Typ)

Strany 8

TTTSSS666444MMMSSSSSS666444VVV666LLL 144PIN PC133 Unbuffered SO-DIMM512MB With 32M X 8 CL3 AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to

Strany 9

TTTSSS666444MMMSSSSSS666444VVV666LLL 144PIN PC133 Unbuffered SO-DIMM512MB With 32M X 8 CL3 SIMPLIFIED TRUTH TABLE COMMAND CKEn-1 CKEn /CS /RAS /CAS

Strany 10

TTTSSS666444MMMSSSSSS666444VVV666LLL 144PIN PC133 Unbuffered SO-DIMM512MB With 32M X 8 CL3 Serial Presence Detect Specification Serial Presence Detec

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